In communication technology where different coding schemes are used it is important to synchronize communication data with a decoder in order to extract useful data. One of the components that are part of this synchronization process is a phase-lock loop (PLL) circuit.
For example, in telecommunication, the phase-Lock Loop (PLL) is used to generate clocks that have fixed phase/frequency relationship with the input reference clock. A typical PLL system is a negative control system comprising a Phase Frequency Detector (PFD), a voltage control oscillator (VCO) and a feedback path. The PFD detects the frequency and phase error between the input reference clock and the feedback clock. Then the error signal will be used to adjust the VCO so that the phase/frequency of the output/feedback clock will be suitably close to the reference clock, which is said to then lock to the reference clock.
In many applications a charge pump Phase-lock loop (PLL) circuit is used. The charge pump PLL comprises a Phase-Frequency Detector (PFD), a Charge Pump, a Loop Filter and a Voltage Control Oscillator (VCO). The widely used PFD in charge pump PLL comprise a comparison between the reference clock and a feedback clock where UP or DOWN signals are generated in the comparison and used to provide output control signal to VCO in order to increase/reduce the frequency of the output of the VCO, which in turn is the feedback clock.
A phase-locked loop solution based on a charge-pump is for instance described in “Charge-Pump Phase-Lock Loops” in IEEE Transactions on Communications, vol. com-28, no. 11, November 1980 and a general description of phase-locked loops may be found in “Phase-Locked Loops: A Control Centric Tutorial” from the Proceedings of the 2002 ACC. These may provide a basic understanding of PLL circuits and their applications.
The typical phase frequency detector has some drawbacks, such as:    1. The output control signals are essentially analogue signals, which can not be used in all-digital PLLs;    2. Given a constant frequency error between the reference clock and the feedback clock, the error signal produced by the PFD is not constant for each phase/frequency comparison, but time-varying. It will result in an inconstant frequency change rate during turning the VCO;    3. The PFD has an over-control problem which may cause the feedback clock to oscillate around the reference clock in a large scale;
In the typical PFD, a UP signal will increase the frequency of the VCO, and a DOWN signal will decrease the frequency VCO. Exemplifying the over-control problem, assuming at the beginning, the frequency of the reference clock is smaller than the frequency of the feedback clock: the PFD generates a DOWN signal to reduce the frequency of the feedback clock. After a certain time, the frequency of the reference clock will become larger than the feedback clock. However, the PFD has a hysteresis effect in that the down signal can not immediately be reduced to zero, but slowly become narrower and narrower and finally disappears. The redundant down signal will cause over reduction of the frequency of the feedback clock, and cause a feedback clock oscillation. Similarly, if the frequency of the reference clock is larger than the frequency of the feedback clock at the beginning, the UP signal will act with the same behaviour as the above described DOWN signal.